I. Field of the Disclosure
The technology of the disclosure relates generally to integrated circuit (IC) cells fabricated using self-aligned quadruple patterning (SAQP), and particularly to reducing the area of SAQP-based IC cells.
II. Background
Integrated circuits (ICs) can be fabricated using various types of process technologies. One such process technology is referred to as light-based lithography, which uses photoresist material and light of a particular wavelength to etch patterns in an IC. In particular, light-based lithography involves disposing a circuit material to be etched, such as metal, over a semiconductor substrate, such as silicon. A photoresist material is disposed over the circuit material in a manner that causes the photoresist material to shield portions of the circuit material corresponding to a desired pattern. The portions of the circuit material not shielded by the photoresist material are then etched using a light source with a particular wavelength. After the portions of the circuit material have been etched, the photoresist material is removed such that the remaining circuit material forms the desired pattern corresponding to that portion of the IC.
However, conventional light-based lithography processes have particular area constraints attributable to the wavelength of the light source used to etch the circuit material. In particular, the smallest achievable metal pitch is limited by the available wavelength. For example, when etching with a light source having a wavelength equal to forty (40) nanometers (nm), the smallest achievable metal pitch is equal to eighty (80) nm. Such a metal pitch limits how small an IC may be fabricated using light-based lithography. Thus, the area reduction limitations of light-based lithography pose a problem as demands for area reduction of ICs continues to increase.
In this regard, other process technologies not limited by light wavelength may be employed so as to achieve a smaller metal pitch, and thus, a smaller area. For example, self-aligned quadruple patterning (SAQP) is one alternative to light-based lithography that can achieve a metal pitch approximately 75% smaller than a metal pitch of light-based lithography. SAQP involves the use of multiple spacers to determine where particular portions of circuit material, such as metal, are to be disposed. In particular, circuit material layers, such as metal layers, are disposed over routing tracks formed between multiple spacers. However, while SAQP achieves a smaller metal pitch than light-based lithography, area reduction using conventional SAQP is limited due to metal line and voltage rail sizing limitations. Thus, it would be advantageous to achieve the reduced metal pitch of SAQP while also further reducing area of corresponding ICs.